In the present day, device fabrication, such as semiconductor device fabrication, may the use of one or multiple sacrificial mask layers, or sacrificial masks, including so-called hard masks. During removal of a mask such as a hard mask, portions of a device may be exposed to a harsh etchant used for mask removal. As an example, during three dimensional NAND memory device (3D NAND) fabrication, a memory array may be exposed to the etchant used to remove hard mask material. While the etchant may be designed to remove the hard mask at a target etch rate using a target recipe, the target recipe may also attack the memory array, resulting in degraded performance of yield. For example, the target recipe may entail high temperature etching effective to remove a carbon-based hard mask. By reducing the etch temperature, attack of the memory by the etchant may be reduced or prevented, while the resulting etch rate of the hardmask may also be reduced below the target etch rate.
With respect to these and other considerations the present disclosure is provided.